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A binary multiplier is an electronic circuit used in digital electronics, such as a computer, to multiply two binary numbers. It is built using binary adders. A variety of techniques can be used to implement a digital multiplier. Most techniques involve computing a set of ''partial products'', and then summing the partial products together. This process is similar to the method taught to primary schoolchildren for conducting long multiplication on base-10 integers, but has been modified here for application to a base-2 (binary) numeral system. ==History== Until the late 1970s, most minicomputers did not have a multiply instruction, and so programmers used a "multiply routine"〔 "The Evolution of Forth" by Elizabeth D. Rather et al. () () 〕〔 ("Interfacing a hardware multiplier to a general-purpose microprocessor" ) 〕 which repeatedly shifts and accumulates partial results, often written using loop unwinding. Mainframe computers had multiply instructions, but they did the same sorts of shifts and adds as a "multiply routine". Early microprocessors also had no multiply instruction. Though the multiply instruction is usually associated with the 16-bit microprocessor generation, at least two "enhanced" 8-bit micro have a multiply instruction: the Motorola 6809, introduced in 1978, and the modern Atmel AVR 8bit microprocessors present in the ATMega, ATTiny and ATXMega microcontrollers. As more transistors per chip became available due to larger-scale integration, it became possible to put enough adders on a single chip to sum all the partial products at once, rather than reuse a single adder to handle each partial product one at a time. Because some common digital signal processing algorithms spend most of their time multiplying, digital signal processor designers sacrifice a lot of chip area in order to make the multiply as fast as possible; a single-cycle multiply–accumulate unit often used up most of the chip area of early DSPs. 抄文引用元・出典: フリー百科事典『 ウィキペディア（Wikipedia）』 ■ウィキペディアで「binary multiplier」の詳細全文を読む スポンサード リンク
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